1. Field of the Invention
The present invention relates to a reconfigurable logic block (RLB), a programmable logic device that is provided with an RLB, and a method of fabricating an RLB, and, in particular, to a technique of fabricating an RLB that enables a reduction in implementation area.
2. Description of the Related Art
Programmable logic devices have recently attracted attention as devices that a user can use to implement logic circuits to suit various different requirements, by electrically programming the internal circuitry thereof. Programmable logic devices (PLDs), field programmable gate arrays (FPGAs), dynamically reconfigurable processors (DRPs), or digital application processor/distributed network architecture (DAP/DNA) devices are known as examples of such programmable logic devices. In addition to being used in the trial manufacture of hardware, they are also used in themselves for configuring large-scale circuits (such as microprocessors) having various different functions.
In order to improve the capabilities of programmable logic devices, new reconfigurable logic block (RLBs) have become necessary. In other words, the RLBs that configure prior-art programmable logic devices can be considered within two frameworks: fine-grained and coarse-grained type.
More specifically, an FPGA or the like can use an RLB as the basis of a look-up table (LUT) employing the fine-grain approach, or a DRP or DAP/DNA or the like can use an RLB as the basis of an arithmetic and logical unit (ALU).
In this case, the LUT is configured of memory, making it possible to implement any desired logic circuit, the number of bits N of input signals of logic circuits that can be implemented corresponds to the number of bits of memory addresses configuring the LUT, and a one-bit signal is output as an output therefrom. Thus a logic circuit that can be implemented in one LUT is an arbitrary N-input, 1-output logic circuit. Note that this kind of LUT is represented by an N-input LUT (N-LUT) in this document.
The fine-grain approach is superior for logical operations in bit units, with methods using LUTs in RLBs, and the coarse-grain approach is superior for arithmetic operations in byte units, with method using ALUs in RLBs.
In the prior art, Japanese Unexamined Patent Publication (Kohyo) No. 2002-511173 proposes an integrated circuit in which the effective area efficiency has been improved even with standard mutual connections, by mixing arithmetic and logic cells, as a method of providing reconfigurable calculation rules that enable flexibility of software development and the capability of solutions by dedicated hardware.
In addition, Japanese Unexamined Patent Publication (Kokai) No. 10-111790 of the prior art proposes a device wherein components such as an accumulator, multiplier and adder are efficiently implemented within one compact cell, as an operation cell configured of a multiplexer and a steering logic circuit for controlling the same. The steering logic circuit receives configuration signals in accordance with the application to control the multiplexer and select a path.
Furthermore, Japanese Unexamined Patent Publication (Kokai) Nos. 11-024891 and 11-122096 of the prior art propose a programmable function block provided with a full adder and front logic, as means of providing a programmable function block that is fast and is also multi-function.
Additionally, Japanese Unexamined Patent Publication (Kokai) No. 2003-018000 of the prior art proposes a method of fabricating an LUT that is provided with a plurality of LUT units and an internal configuration control means that controls the internal configuration created by that plurality of LUT units, in an FPGA.
As described above, since a prior-art device such as an FPGA based on a fine-grained LUT is inferior for implementing an arithmetic circuit, another component such as a multiplier is mounted separately, and thus the area efficiency (implementation efficiency) of the chip is reduced by that amount.
Similarly, a device such as a DRP or DAP/DNA based on a coarse-grained type ALU has a bad area efficiency when used to configure a random logic (glue logic) circuit. More specifically, any deterioration of capabilities is avoided by having an arithmetic-logic unit that is called a data management unit (DMU) in addition to the ALU, but if this arithmetic-logic unit is not used, that in itself will be a cause of a drop in area efficiency. This makes it impossible to prevent deterioration in the area efficiency of the chip.
More specifically, since an adder circuit of the operation cell disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-111790 is configured of an two 8-LUTs, by way of example, and the two LUTs are not connected internally, the original capability thereof as an adder is insufficient from the viewpoints of both area efficiency and speed. In addition, since each RLB of the operation cell disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-111790 is configured of two 8-LUTs during logical operations, the area efficiency thereof is even worse.
The programmable function block disclosed in Japanese Unexamined Patent Publication (Kokai) No. 11-024891 by way of example is provided with a one-bit full adder and front logic within each RLB, but since carries are through external wiring during operations with a plurality of bits, problems arise in that speed overheads increase and completion of the logic cannot be ensured during logical operations.